1. Field of the Invention
The present invention relates generally to an image pickup apparatus. More particularly, the invention relates to an image pick-up apparatus used by being connected to external equipment, such as a personal computer or the like, which apparatus is operable by the clock of a bus for the external equipment so as to output digital chrominance signals to the bus, thereby simplifying the overall construction of the apparatus.
2. Description of the Related Art
Hitherto, personal computers, etc. are adapted to execute image processing by capturing video signals from video equipment, such as a television camera and so on, through an interface board used for video-signal processing.
Namely, FIG. 14 is a block diagram illustrating an image-processing system for use in a personal computer. In this image-processing system generally designated by 1, an interface board 2 used for video-signal processing is inserted into a slot of the personal computer and is connected to a bus of the personal computer. A television camera 3 is then connected to this interface board 2. The television camera 3 employed in this system outputs standard video signals according to the National Television System Committee (NTSC) system or the like. For example, the television camera 3 switches its operation under control of the personal computer through an interface, such as RS232C or the like, and outputs a video signal SV representing image pick-up results to a video terminal T1 of the interface board 2.
The interface board 2 inputs this video signal SV into a decoder 4 which then separates a horizontal synchronizing signal HD from the video signal SV with the use of its built-in synchronous separation circuit. The decoder 4 also divides the video signal SV into a luminance signal (Y signal) and a color difference signal (C signal) in its built-in Y/C separation circuit. Then, the decoder 4 further converts the luminance signal and the color difference signal into a red-color signal R, a green-color signal G and a blue-color signal B in a predetermined matrix computation circuit.
A phase locked loop (PLL) circuit 5 generates a clock CK1 having a predetermined frequency, based on the horizontal synchronizing signal HD that is output from the decoder 4, and then, outputs it. Analog-to-digital (A/D) conversion circuits 6R, 6G and 6B, relative to this clock CK1, digitize the red-color signal R, the green-color signal G and the blue-color signal B which are then respectively converted into 8-bit digital chrominance signals.
First In First Out (FIFO) storages 7R, 7G and 7B incorporate the digital chrominance signals that are output from the A/D conversion circuits 6R, 6B and 6B, respectively, at a timing in synchronization with the digital chrominance signals, and then output them to the internal BUS at a timing in synchronization with a clock CK2 of the BUS. With this arrangement, after the image-processing system of the above type thus converts the video signal SV obtained from a typical television camera into digital chrominance signals suitable for personal-computer processing, it outputs the signals to the personal computer at a timing in synchronization with the internal BUS.
In this type of image-processing system, it may be convenient and further increase ranges of uses for applications of personal computers of the above type if the overall construction of the image processing system is simplified.